1. Field
Various embodiments of the present invention relate generally to a complementary metal oxide semiconductor (CMOS) image sensor and, more particularly, a latch circuit, a double data rate ring counter based on the latch circuit, a hybrid counting device employing the double data rate ring counter, an analog-to-digital converting device employing the hybrid counting device, and a CMOS image sensor employing the analog-to-digital converting device.
2. Description of the Related Art
In a counter structure where a certain period of a pulse signal, e.g., a comparator output signal, is counted by using a reference clock or a counter clock in a CMOS image sensor, for example, power consumption may increase generally in proportion to the number of toggles in the counter.
For example, in a case where a 10-bit binary counter, such as a typical ring counter, carries out a full counting and each of the latch circuits in the counter is designed based on two flip-flops connected in cascade, the counter may have 2046 toggles including 512*2 toggles in a first least significant bit (LSB), 256*2 toggles in a second LSB, 128*2 toggles in a third LSB, 64*2 toggles in a fourth LSB, 32*2 toggles in a fifth LSB, 16*2 toggles in a sixth LSB, 8*2 toggles in a seventh LSB, 4*2 toggles in a eighth LSB, 2*2 toggles in a ninth LSB, and 1*2 toggles in a most significant bit (MSB).
Since the number of toggles in a lower-bit portion may be much greater than in an upper-bit portion so, for example, 1792 toggles of the 2046 toggles may be concentrated in three lowermost bit positions, much power may be consumed in the stages corresponding to the lower-bit portion.